Schrodinger&#x27;s instruction: simultaneously defined and undefined

&gt; Better to stick with ud2. Its behavior is consistent and architecturally guaranteed.Ah, finally an undefined instruction whose behaviour is consistent and architecturally guaranteed!

Tangential, but I almost never read assembly [1], but I do read Java bytecode pretty frequently, primarily because doing that can sometimes be a good substitute for benchmarking [2], which I do not enjoy.The thing that never seems to stop tripping me up is the different “dup” codes that compile. At some point I really need to properly learn the difference between dup_x2 and dup2_x1 and dup2_x2.[1] not out of like an ethical objection, just my career has involved almost no reverse engineering and it’s also never been a path I have been super interested in to pursue on my own.[2] e.g. if two competing chunks of code emit the same bytecode, you don’t need to pull out JMH. My go to example for this is using if statements vs switches, which will usually emit the same code so performance arguments are moot.

0 undoubtedly comes first, but we all know 1 == true...

Thus finally the 0F FF believers were rewarded by being give the honor of op code UD0 making it the one and true original invalid opcode permanently disgracing the 0F B9 adherents with the shame of UD1.

Couldn&#x27;t find UDW in the intel docs - <a href="https:&#x2F;&#x2F;intel.github.io&#x2F;SDM&#x2F;sdm.html" rel="nofollow">https:&#x2F;&#x2F;intel.github.io&#x2F;SDM&#x2F;sdm.html</a>But found it in wikipedia which is well structured and has detailed notes&#x2F;comments on all instructions - <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;List_of_x86_instructions" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;List_of_x86_instructions</a>

Nowadays UD0 UD1 UD2 are in the SDM and APM.We also got UDB (D6), the one-byte variant that arrived with x86-64 for 64-bit mode.And we have always had UDW (FF FF), aka group #5 (1st FF) with a modrm byte of mod=11b r&#x2F;m=111b (&#x2F;7) reg=111b (2nd FF) -- that one matters for memory with all bits set to 1, or for buses terminated to all 1 when no device claims an access.

Hyrum’s Law reaching all the way down to the instruction decoder. And for those who care the ud2 opcode is 0F 0B

#UD has the same stack frame as a software interrupt, there&#x27;s no error code pushed. But most likely, executing INT 06 from ring 3 will generate a protection fault instead, since the gate descriptor would be set up to not be reachable from that privilege level.(exceptions that do push an error code couldn&#x27;t be emulated at all using INT, since the error code is the last thing pushed by the CPU, after flags and return address)

&gt; the INT instruction alone is not enough for this, but you need to setup the stack in such a way so that it will contain the information expected by the exception handler,Wait, what? The x86 CPUs construct the stack frame themselves before jumping to the interrupt handler, otherwise e.g. INT3 wouldn&#x27;t work.

Already since Intel 8086, x86 has the instruction &quot;INT vector_number&quot;, whose purpose is to allow software to invoke directly any of the many kinds of exception handlers or hardware interrupt handlers that are specified by the ISA or implemented by the hardware designer, which are normally invoked when various conditions arise, as determined by software execution or by I&#x2F;O events.So you can invoke the handler of the invalid instruction exception with the INT instruction, but as another poster mentioned, the INT instruction alone is not enough for this, but you need to setup the stack in such a way so that it will contain the information expected by the exception handler, which requires multiple instructions.This kind of invocation may be acceptable when you write a test program for the invalid instruction exception handler, but it is not acceptable when you want to initialize some guard memory with values that will trigger the exception, to signal that your program has attempted to execute instructions from an area that should not be executable. Setting a memory area as non-executable through the access rights has only page granularity, so it is not useful when a page must contain both some executable code and some non-executable data.If Intel had not defined an official opcode that is guaranteed to remain unused forever, to be able to reliably trigger the invalid instruction exception, the workaround would have been for the user to reserve one of the 256 interrupt vectors for the invocation through software of the invalid instruction exception. For that vector, a simple handler could have been used, which would have setup the stack in the right way, before jumping to the invalid instruction handler.But this workaround would have had the disadvantage that any chosen interrupt vector could have conflicted with some choice made by the hardware designers of some computers, so it would have been required for it to be a configurable parameter of the operating system kernel, and also of the user applications that need it, like compilers, unless it would have been standardized by some organization.Just reserving an opcode at Intel and AMD was simpler, with no other requirements for standardization or changes in the existing software.

And this is code that will (hopefully) almost never run, so you don&#x27;t want it to take up much space in you your program, and especially cache lines.

Maybe because if the code wants to call the invalid opcode interrupt handler (INT6), it needs extra code to populate the flags and registers expected by that handler, whereas actually triggering an invalid opcode exception will get all those parameters populated automatically.

There&#x27;s a bit of convention and practicality The only thing you really need is that your &quot;fatal error&quot; instruction and &quot;syscall&quot; instruction can be reasonably discriminated without needing to set registers at the call site. Needing to set register to identify a fatal error is not great for code size, especially in languages that generate a lot of them (memory safe languages, mostly).Though, yes, convention does play a role. On ARMv8 you get both SVC &lt;imm&gt; and BRK &lt;imm&gt;. SVC and BRK raise different exception codes (which satisfies the &quot;easy to distinguish requirement) but in principle you could just use BRK with a well-known immediate and eliminate the need for SVC since BRK&#x27;s immediate is reported in the exception status register. And, anyways, if you have an SVC instruction and a BRK instruction, you may as well use the SVC instruction for syscalls since it&#x27;s right there.

It&#x27;s basically a convention. The alternative is to raise interrupts of course, but that might be application specific, or use other invalid instructions than the designated one, but they might work differently on other processor types.

It&#x27;s common to use int3 for some of the scenarios mentioned in the article. (Like non-reachable code) This instruction is often used to trigger a break in the debugger.

An interrupt or SYSCALL instruction could do anything, which includes remapping or overwriting the memory location it returns to. So no, these instructions can&#x27;t be prefetched in any case.

I expect that UD2 stops instruction fetching (beyond the current block) and conversion to µops. A software interrupt or supervisor call should probably do neither because most of the time, these instructions eventually return and continue executing the next instruction.

&gt;you can raise software interrupts&#x2F;exceptionsexception handling requires that some unrelated region of memory is initialized and intact and ready to do the right thing, whatever that is, and that region is outside the scope of your control, it belongs to the operating system or the the embedded ROM, and it may not have been laid out to take care of your case.assembly&#x2F;machine code is operating at a lower layer: &quot;I don&#x27;t know what larger thing I&#x27;m a part of, but I know I need to stop.&quot;

x86 has...INT Ib
INT1
INT3
INTO
BOUND

I&#x27;m not much of an x86 person but on other architectures you can raise software interrupts&#x2F;exceptions. Does x86 not have this or did those facilities not cover enough use cases?

I recently had to debug builds that failed randomly and a ud2 from V8 was there waiting for me.

What the instruction does is well documented, and the history of other invalid instructions being used for the same purpose in the past I&#x27;m guessing there is also well known, though a quick search doesn&#x27;t turn up any official Intel documentation on the matter.Given who this is and the overall quality of his output over the years, I&#x27;m willing to trust it isn&#x27;t pure guesswork - and anyway, I&#x27;d trust his guesswork over many other people&#x27;s absolute facts.

This is a first hand account of somebody very knowledgeable and respected in the industry at the time of the events. I would say he is the evidence.

Is this just his speculation? Or is there evidence for it?

A: and B: were not specific to the type of drive. It was common to have two drives before fixed storage became common, often you would have the application disk in one and your data disk in the other though there were other common use patterns for two drives also (with the OS, or at least the core of it, resident in memory you can copy and otherwise manage data over two data disks, and so on).The first hard-drive in a system was made C: to reserve A: and B: in part because there was software out there that assumed A: and B: were floppy drives and could cause problems if something else was allocated to those signifiers. There are many things that are due to long forgotten compatibility issues like this (try naming file LPT1 under Windows to see another). Another reason is that the BIOS on many PCs was just hard-wired to assume two floppy drives so DOS would see that even if there were no drives really there.

Even further back into time, before 3.5&quot; disks, both A: and B: were 5.25&quot; disks. And, although my memory is hazy, 3.5&#x27;s were commonly slotted into B: at first, because no one had 3.5&quot; boot disks until the drives became somewhat common.

Yeah it&#x27;s a relic from when computers booted off floppy and hard disks were rare and expensive

MS-DOS didn&#x27;t have built in support for 3.5&quot; drives until version 3.2.

A: drive is 3.5; B: drive is 5.25; C: drive is hard disk

It&#x27;s like why the first (hard) drive letter is C.

&gt; It’s called ud2 because the 0F FF variant was retroactively named ud0, and the 0F B9 variant was retroactively named ud1, leaving ud2 as the recommended undefined opcode.It was a surprise for me as a reader. When I came to this sentence I assumed that 0f ff would become #1 and 0fb9 -- #2. But no, Intel counts from zero, so there is a third ud.

Why is the x86 undefined instruction called ud2? Why 2?