> Little of the detail of this path is documented by NVIDIA, at least not to the level that we’d like, so we’ll determine it by running timing experiments on the hardware itself
Or you could just use the AMD isa.
yipinwong
This is a type of article that is HN worthy and came to HN for initially because I don't even understand a third of content there. Giving me inspiration to dive deeper.
SEriously, I don't understand it (yet) lol.
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empiricus
For a long time, the chip manufacturers had an inclination to simplify the hardware and rely on the software adapting and optimizing. But for decades this bid failed. Now we have the unrelenting AI capable of finetuning kernels relatively quickly. Maybe simpler hw will work this time? Note: not sure if TPU/NPU is not only simple but also too limited.
> Little of the detail of this path is documented by NVIDIA, at least not to the level that we’d like, so we’ll determine it by running timing experiments on the hardware itself
Or you could just use the AMD isa.
This is a type of article that is HN worthy and came to HN for initially because I don't even understand a third of content there. Giving me inspiration to dive deeper.
SEriously, I don't understand it (yet) lol.
For a long time, the chip manufacturers had an inclination to simplify the hardware and rely on the software adapting and optimizing. But for decades this bid failed. Now we have the unrelenting AI capable of finetuning kernels relatively quickly. Maybe simpler hw will work this time? Note: not sure if TPU/NPU is not only simple but also too limited.
VERY good article, reminds me on:
"what every programmer should know about memory" https://github.com/Ty-Chen/Reading-List/blob/master/What%20e...
Can someone help me understand why I spent 5 minutes reading something that I still don't understand?
Link for the ELI5 version?
YMMV; not all GPUs work exactly like this
Ctrl+F PCIe BAR.. nothing.