Love your commitment to this. You are doing excellent work to keep Wirth's computing spirit alive. Oberon's philosophy ( https://people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf ) is beautiful for the power it hides behind its simplicity and I wish it was a more popular language ...
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clbrmbr
Would it be practical to have the ESP P4 self-host?
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tosh
what does RISC-V instead of RISC-5 mean?
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OCTAGRAM
> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM)
If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.
Readers encountering this project for the first time should be aware that the earlier Oberon-on-RISC-V project <https://github.com/solbjorg/oberon-riscv> (HN discussion: <https://news.ycombinator.com/item?id=25497002>) exists and was already discussed on the mailing list:
<https://lists.inf.ethz.ch/pipermail/oberon/2026/017161.html>
Love your commitment to this. You are doing excellent work to keep Wirth's computing spirit alive. Oberon's philosophy ( https://people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf ) is beautiful for the power it hides behind its simplicity and I wish it was a more popular language ...
Would it be practical to have the ESP P4 self-host?
what does RISC-V instead of RISC-5 mean?
> The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM)
If somebody wants their FPGA work to be available, they better choose MiSTer FPGA from the beginning. Costlier, but way more likely to be found around.