254K prefixes with skewed distribution means early exits dominate, and no SIMD throughput advantage survives a branch that terminates at depth 3. The interesting edge case is deaggregation events where prefix counts spike transiently and the rebuild-and-swap FIB has to absorb a table that&#x27;s temporarily 2x normal size

I likewise wonder from time to time whether I should replace WireGuard&#x27;s allowedips.c trie with something better: <a href="https:&#x2F;&#x2F;git.kernel.org&#x2F;pub&#x2F;scm&#x2F;linux&#x2F;kernel&#x2F;git&#x2F;torvalds&#x2F;linux.git&#x2F;tree&#x2F;drivers&#x2F;net&#x2F;wireguard&#x2F;allowedips.c" rel="nofollow">https:&#x2F;&#x2F;git.kernel.org&#x2F;pub&#x2F;scm&#x2F;linux&#x2F;kernel&#x2F;git&#x2F;torvalds&#x2F;lin...</a>

The obvious question, I guess: How much faster are you than whatever is in the Linux kernel&#x27;s FIB? (Although I assume they need RCU overhead and such. I have no idea what it all looks like internally.)

I wonder if this would port nicely over to rustybgp.

Clean-room, portable C++17 implementation of the PlanB IPv6 LPM algorithm.Includes:
- AVX-512 SIMD path + scalar fallback
- Wait-free lookups with rebuild-and-swap dynamic FIB
- Benchmarks on synthetic data and real RIPE RIS BGP (~254K prefixes)Interesting result: on real BGP + uniform random lookups, a plain Patricia trie can sometimes match or beat the SIMD tree due to cache locality and early exits.Would love feedback, especially comparisons with PopTrie &#x2F; CP-Trie.

It actually does detect it using ifdef [0] but uses cmake stuff to avoid passing &quot;-mavx512&quot; kind of flags to the compiler [1].[0] <a href="https:&#x2F;&#x2F;github.com&#x2F;esutcu&#x2F;planb-lpm&#x2F;blob&#x2F;748d19d5fbd945cefa3c2b31c3c0f55c50858989&#x2F;include&#x2F;lpm6.hpp#L22" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;esutcu&#x2F;planb-lpm&#x2F;blob&#x2F;748d19d5fbd945cefa3...</a>[1] <a href="https:&#x2F;&#x2F;github.com&#x2F;esutcu&#x2F;planb-lpm&#x2F;blob&#x2F;748d19d5fbd945cefa3c2b31c3c0f55c50858989&#x2F;CMakeLists.txt#L15" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;esutcu&#x2F;planb-lpm&#x2F;blob&#x2F;748d19d5fbd945cefa3...</a>

Why detect avx512 in build system instead of using #ifdef ?

The lines<pre><code> __m512i vx = _mm512_set1_epi64(static_cast&lt;long long&gt;(x));
 __m512i vk = _mm512_load_si512(reinterpret_cast&lt;const __m512i*&gt;(base));
 __mmask8 m = _mm512_cmp_epu64_mask(vx, vk, _MM_CMPINT_GE);
 return static_cast&lt;std::uint32_t&gt;(__builtin_popcount(m));
</code></pre>
would be replaced with:<pre><code> return __riscv_vcpop(__riscv_vmsgeu(__riscv_vle64_v_u64m1(base, FANOUT), x, FANOUT), FANOUT);
</code></pre>
and you set FANOUT to __riscv_vsetvlmax_e32m1() at runtime.Alternatively, if you don&#x27;t want a dynamic FANOUT you keep the FANOUT=8 (or another constant) and do a stripmining loop<pre><code> size_t cnt = 0;
 for (size_t vl, n = 8; n &gt; 0; n -= vl, base += vl) {
 vl = __riscv_vsetvl_e64m1(n);
 cnt += __riscv_vcpop(__riscv_vmsgeu(__riscv_vle64_v_u64m1(base, vl), x, vl), vl);
 }
 return cnt;
</code></pre>
This will take FANOUT&#x2F;VLEN iterations and the branches will be essentially almost predicted.If you know FANOUT is always 8 and you&#x27;ll never want to changes it, you could alternatively use select the optimal LMUL:<pre><code> size_t vl = __riscv_vsetvlmax_e32m1();
 if (vl == 2) return __riscv_vcpop(__riscv_vmsgeu(__riscv_vle64_v_u64m4(base, 8), x, 8), 8);
 if (vl == 4) return __riscv_vcpop(__riscv_vmsge(u__riscv_vle64_v_u64m2(base, 8), x, 8), 8);
 return __riscv_vcpop(__riscv_vmsgeu(__riscv_vle64_v_u64m1(base, 8), x, 8), 8);</code></pre>

I wonder how this would look like in risc-v vector instructions

&gt; It does look a bit AI generated thoughThese days, when I hear a project owner&#x2F;manager describe the project as a &quot;clean room reimplementation&quot;, I expect that they got an LLM [0] to extrude it. This expectation will not always be correct, but it&#x27;ll be correct more likely than not.[0] ...whose &quot;training&quot; data almost certainly contains at least one implementation of whatever it is that it&#x27;s being instructed to extrude...

Why? It is 500 lines of pretty basic code. You can port it if you don&#x27;t like C++ to any language, assuming you understand what it is.It does look a bit AI generated though

A cache-friendly IPv6 LPM with AVX-512 (linearized B+-tree, real BGP benchmarks)